1. Field of the Invention
The present invention relates in general to the field of virtualized information handling systems, and more particularly to a system and method for distributed address translation in virtualized information handling system.
2. Description of the Related Art
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Information handling systems sometimes run plural virtual machines on a common hardware platform to support multiple users or multiple functions. Each virtual machine running on an information handling system platform typically has its own operating system which shares system resources with other operating systems, such as processor an memory resources. For example, physical input/output (I/O) devices are virtualized to allow shared physical access by the virtual machines to the physical I/O devices. The Directed I/O architecture of Intel Corporation and the IOMMU architecture of AMD each make provisions for translation of “guest” physical addresses associated with virtual machines to host physical addresses in the information handling system Root Complex (RC). In these architectures, a translation agent (TA) acts as a centralized logical entity in the RC that translates addresses generated from bus mastering DMA I/O devices to coordinate physical accesses to memory locations for virtualized I/O devices. The translation agent typically includes an access rights check to ensure that the DMA device is allowed to access the referenced memory locations. FIG. 1 depicts the presently contemplated architecture for centralized DMA address translations where an information handling system platform 10 supports plural virtual machines (VMs) 12. A virtual machine monitor (VMM) 14 running on a processor 16 establishes and revokes mappings to a memory 18 through a memory hub 20 through a translation agent 22 associated with memory hub 20. The centralized translation agent 22 coordinates accesses by virtual machines 12 to memory locations associated with I/O hub 24 and I/O devices 26.
Several difficulties arise with centralized DMA address translation in a host information handling system, as is depicted by FIG. 1. For instance, DMA access time is sometimes substantially lengthened due to the time involved in resolving physical addresses. In implementations that access a main memory-resident translation table, access times are typically significantly longer than the access times for untranslated accesses. Where a DMA transaction uses multiple memory accesses, such as for a table walk, then the memory transaction rate or overhead associated with the DMA transaction is often high. To mitigate these difficulties, the PCI-SIG IO workgroup has defined mechanisms that allow an I/O device to implement Address Translation Caches (ATC) similar to Translation Look-aside Buffers (TLB) associated with CPU accesses. However, the effectiveness of the ATC approach varies based on system configuration and usage models. The ATC approach is hampered because the centralized translation agent architecture does not scale well and offers a single point of failure in an information handling system. Generally, centralized translation agent control of device-to-device accesses is inefficient.